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W948D6FB / W948D2FB
256Mb Mobile LPDDR
6.2.2 Mode Register Definition
BA1
BA0
An..A7 (see Note 1)
A6
A5
A4
A3
A2
A1
A0
Address Bus
0
0
0 (see Note 2)
CAS Latency
BT
Burst Length
Mode Register
A6
0
0
0
0
1
1
1
1
A5
0
0
1
1
0
0
1
1
A4
0
1
0
1
0
1
0
1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
A3
0
1
Burst Type
Sequential
Interleave
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
Burst Length
Reserved
2
4
8
16
Reserved
Reserved
Reserved
NOTE:
1.MSB depends on LPDDR SDRAM density.
2.Alogic 0 should be programmed to all unused / undefined address bits to future compatibility.
6.2.3. Burst Length
Read and write accesses to the LPDDR SDRAM are burst oriented, with the burst length and burst type being
programmable.
The burst length determines the maximum number of column locations that can be accessed for a given READ or
WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst
types.
When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All
accesses for that burst take place within the block, meaning that the burst will wrap within the block if a boundary is
reached.
The block is uniquely selected by A1 ? An when the burst length is set to two, by A2 ? An when the burst length is set
to 4, by A3 ? An when the burst length is set to 8 (where An is the most significant column address bit for a given
configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the
block. The programmed burst length applies to both read and write bursts.
Publication Release Date : Oct, 15, 2012
- 13 -
Revision : A01-004
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